8L( 'tsd,px30-ringneck-haikourockchip,px30 +07Theobroma Systems PX30-uQ7 SoM on Haikou devkitaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff390000/mmc@ff380000/i2c@ff190000/rtc@6f/i2c@ff180000/pmic@20/ethernet@ff360000/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZ  +cpu@1cpuarm,cortex-a35psciZ  +cpu@2cpuarm,cortex-a35psciZ  + cpu@3cpuarm,cortex-a35psciZ  + idle-states3pscicpu-sleeparm,idle-state@Qhxy+cluster-sleeparm,idle-state@Qhy+opp-table-0operating-points-v2+opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkin%psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal2HVh tripstrip-point-0xppassivetrip-point-1xLpassive+soc-critx8 criticalcooling-mapsmap0 gpu-thermal2dHh tripsgpu-thresholdxppassivegpu-targetxLpassive+gpu-critx8 criticalcooling-mapsmap0 xin24m fixed-clock%n6xin24m+gpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller++ipower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd++io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB  RBRB$RBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&2baudclkapb_pclk>''CtxrxMWddefaultr(okayi2s@ff060000rockchip,px30-i2s-tdm  2mclk_txmclk_rxhclk>''Ctxrx|) tx-mrx-mddefaultr*+,-okay+i2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  2i2s_clki2s_hclk>''Ctxrxddefaultr./01 disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s 2i2s_clki2s_hclk>''Ctxrxddefaultr2345 disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   +syscon@ff140000$rockchip,px30-grfsysconsimple-mfd++)io-domains rockchip,px30-io-voltage-domainokay%6 %%&%47B%lvdsrockchip,px30-lvdsV8[dphy|)elvds disabledports+port@0+endpoint@0u9+endpoint@1u:+port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I2baudclkapb_pclk>''CtxrxMWddefault r;<= disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J2baudclkapb_pclk>''CtxrxMWddefaultr> disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K2baudclkapb_pclk>''CtxrxMWddefault r?@A disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L2baudclkapb_pclk>'' CtxrxMWddefault rBCD disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M2baudclkapb_pclkMWddefaultrEFokay G i2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN 2i2cpclk ddefaultrH+okaypmic@20rockchip,rk809  GrIddefault%xin32kJJJJ%%%JregulatorsDCDC_REG1vdd_log-~Ep]qrregulator-state-mem~DCDC_REG2vdd_arm-~Ep]qr+regulator-state-mem~DCDC_REG3vcc_ddrrregulator-state-memDCDC_REG4 vcc_3v0_1v8-w@E-r+7regulator-state-mem-DCDC_REG5vcc_3v3-2ZE2Zr+%regulator-state-mem2ZLDO_REG2vcc_1v8-w@Ew@r+fregulator-state-memw@LDO_REG3vcc_1v0-B@EB@rregulator-state-memB@LDO_REG5 vccio_sd-w@E2Zr+6regulator-state-mem2ZLDO_REG7r-B@EB@vcc_lcdregulator-state-memB@LDO_REG8 vcc_1v8_lcd-w@Ew@rregulator-state-memw@LDO_REG9 vcca_1v8-w@Ew@rregulator-state-memw@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO 2i2cpclk ddefaultrK+okayfan@18 ti,amc6821rtc@6f isil,isl1208oi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP 2i2cpclk  ddefaultrL+okaycodec@a fsl,sgtl5000 MNOP+i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q 2i2cpclk  ddefaultrQ+okayeeprom@50P atmel,24c01 Ospi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U2spiclkapb_pclk>' ' CtxrxddefaultrRSTU+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V2spiclkapb_pclk>''CtxrxddefaultrVWXYZ+okay%[ [ watchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S 2pwmpclkddefaultr\.okaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S 2pwmpclkddefaultr]. disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S 2pwmpclkddefaultr^. disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S 2pwmpclkddefaultr_. disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T 2pwmpclkddefaultr`. disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T 2pwmpclkddefaultra. disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T 2pwmpclkddefaultrb. disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T 2pwmpclkddefaultrc. disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& 2pclktimerdma-controller@ff240000arm,pl330arm,primecell$@9 2apb_pclkP+'tsadc@ff280000rockchip,px30-tsadc( $[,kP,X2tsadcapb_pclk tsadc-apb|)dinitdefaultsleeprdedokay+ saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-W2saradcapb_pclk saradc-apbokayfnvmem@ff290000rockchip,px30-otp)@/Za2otpapb_pclkphyphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ g& 2xin24mgpll|)%8[@IkFq рр +clock-controller@ff2bc000rockchip,px30-pmucru+g2xin24m|)%[&&& kG+&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & 2phyclk%[h usb480m_phyokay+hhost-port D linestateokay+kotg-port$BA@otg-bvalidotg-idlinestateokay+jphy@ff2e0000rockchip,px30-dsi-dphy.& E 2refpclk>apb#i  disabled+8phy@ff2f0000rockchip,px30-csi-dphy/@F2pclk#i /apb|) disabled+usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >2otg1otg9KZ@ Vj [usb2-phy#iokayusb@ff340000 generic-ehci4 <Vk[usb#iokayusb@ff350000 generic-ohci5 =Vk[usb#iokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[2stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed|)irmiiddefaultrlm#i ^ stmmacethokay r[ PP%outputmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD2biuciuciu-driveciu-sampleрddefaultrnopq#iokay6. ?GHSOmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF2biuciuciu-driveciu-sampleрddefault rrst#i  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH2biuciuciu-driveciu-sampleрddefault ruvw#i okay_nxyS%7spi@ff3a0000 rockchip,sfc:@ 8:2clk_sfchclk_sfc ryz{ddefault#i  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 972ahbnfc[7kрddefault r|}~#i  disabledopp-table-1operating-points-v2+opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuI#i okay+video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu 2aclkhclk#i iommu@ff442800rockchip,iommuD( Q 2aclkiface#i +dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD2pclkV8[dphy#i =apb|)+ disabledports+port@0+endpoint@0u+endpoint@1u+port@1vop@ff460000rockchip,px30-vop-bigF M2aclk_vopdclk_vophclk_vop345 axiahbdclk#i  disabledport++ endpoint@0u+endpoint@1u+9iommu@ff460f00rockchip,iommuF M 2aclkiface#i  disabled+vop@ff470000rockchip,px30-vop-litG N2aclk_vopdclk_vophclk_vop789 axiahbdclk#i  disabledport++ endpoint@0u+endpoint@1u+:iommu@ff470f00rockchip,iommuG N 2aclkiface#i  disabled+isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_2ispaclkhclkpclkV[dphy#i  disabledports+port@0+iommu@ff4a8000rockchip,iommuJ F 2aclkiface#i +qos@ff518000rockchip,px30-qossysconQ +qos@ff520000rockchip,px30-qossysconR +$qos@ff52c000rockchip,px30-qossysconR +qos@ff538000rockchip,px30-qossysconS +qos@ff538080rockchip,px30-qossysconS +qos@ff538100rockchip,px30-qossysconS +qos@ff538180rockchip,px30-qossysconS +qos@ff540000rockchip,px30-qossysconT +qos@ff540080rockchip,px30-qossysconT +qos@ff548000rockchip,px30-qossysconT +qos@ff548080rockchip,px30-qossysconT + qos@ff548100rockchip,px30-qossysconT +!qos@ff548180rockchip,px30-qossysconT +"qos@ff548200rockchip,px30-qossysconT +#qos@ff550000rockchip,px30-qossysconU +qos@ff550080rockchip,px30-qossysconU +qos@ff550100rockchip,px30-qossysconU +qos@ff550180rockchip,px30-qossysconU +qos@ff558000rockchip,px30-qossysconU +qos@ff558080rockchip,px30-qossysconU +pinctrlrockchip,px30-pinctrl|)+gpio@ff040000rockchip,gpio-bank &+Ggpio@ff250000rockchip,gpio-bank% \+gpio@ff260000rockchip,gpio-bank& ]bios-disable-override-hog bios_disable_overridebios-disable-n-hog bios_disable gpio@ff270000rockchip,gpio-bank' ^+[pcfg-pull-up +pcfg-pull-down pcfg-pull-none '+pcfg-pull-none-2ma ' 4pcfg-pull-up-2ma  4pcfg-pull-up-4ma  4+pcfg-pull-none-4ma ' 4pcfg-pull-down-4ma  4pcfg-pull-none-8ma ' 4+pcfg-pull-up-8ma  4+pcfg-pull-none-12ma ' 4 +pcfg-pull-up-12ma  4 +pcfg-pull-none-smt ' C+pcfg-output-highpcfg-output-low Xpcfg-input-high  c+pcfg-input ci2c0i2c0-xfer p +Hi2c1i2c1-xfer p+Ki2c2i2c2-xfer p+Li2c3i2c3-xfer p  +Qtsadctsadc-otp-pin p+dtsadc-otp-out p+euart0uart0-xfer p  +(uart0-cts p uart0-rts p uart1uart1-xfer p+;uart1-cts p+<uart1-rts p+=uart2-m0uart2m0-xfer p+>uart2-m1uart2m1-xfer p uart3-m0uart3m0-xfer puart3m0-cts puart3m0-rts puart3-m1uart3m1-xfer p+?uart3m1-cts p +@uart3m1-rts p +Auart4uart4-xfer p+Buart4-cts p+Cuart4-rts p+Duart5uart5-xfer p+Euart5-cts puart5-rts pspi0spi0-clk p+Rspi0-csn p+Sspi0-miso p +Tspi0-mosi p +Uspi0-clk-hs pspi0-miso-hs p spi0-mosi-hs p spi1spi1-clk p+Vspi1-csn0 p spi1-csn1 p spi1-miso p+Yspi1-mosi p +Zspi1-clk-hs pspi1-miso-hs pspi1-mosi-hs p spi1-csn0-gpio-pin p +Wspi1-csn1-gpio-pin p +Xpdmpdm-clk0m0 ppdm-clk0m1 ppdm-clk1 ppdm-sdi0m0 ppdm-sdi0m1 ppdm-sdi1 ppdm-sdi2 ppdm-sdi3 ppdm-clk0m0-sleep ppdm-clk0m1-sleep ppdm-clk1-sleep ppdm-sdi0m0-sleep ppdm-sdi0m1-sleep ppdm-sdi1-sleep ppdm-sdi2-sleep ppdm-sdi3-sleep pi2s0i2s0-8ch-mclk pi2s0-8ch-sclktx p+*i2s0-8ch-sclkrx p i2s0-8ch-lrcktx p++i2s0-8ch-lrckrx p i2s0-8ch-sdo0 p+,i2s0-8ch-sdo1 pi2s0-8ch-sdo2 pi2s0-8ch-sdo3 pi2s0-8ch-sdi0 p+-i2s0-8ch-sdi1 p i2s0-8ch-sdi2 p i2s0-8ch-sdi3 pi2s1i2s1-2ch-mclk pi2s1-2ch-sclk p+.i2s1-2ch-lrck p+/i2s1-2ch-sdi p+0i2s1-2ch-sdo p+1i2s2i2s2-2ch-mclk pi2s2-2ch-sclk p+2i2s2-2ch-lrck p+3i2s2-2ch-sdi p+4i2s2-2ch-sdo p+5sdmmcsdmmc-clk p+nsdmmc-cmd p+osdmmc-det p+psdmmc-bus1 psdmmc-bus4@ p+qsdiosdio-clk p+tsdio-cmd p+ssdio-bus4@ p+remmcemmc-clk p +uemmc-cmd p +vemmc-rstnout p emmc-bus1 pemmc-bus4@ pemmc-bus8 p+wemmc-reset p +flashflash-cs0 p+flash-rdy p +flash-dqs p +flash-ale p +|flash-cle p +~flash-wrn p +flash-csl pflash-rdn p+flash-bus8 p+}sfcsfc-bus4@ p+{sfc-bus2 psfc-cs0 p+zsfc-clk p +ylcdclcdc-rgb-dclk-pin plcdc-rgb-m0-hsync-pin plcdc-rgb-m0-vsync-pin plcdc-rgb-m0-den-pin plcdc-rgb888-m0-data-pins p     lcdc-rgb666-m0-data-pins p     lcdc-rgb565-m0-data-pins p     lcdc-rgb888-m1-data-pins p   lcdc-rgb666-m1-data-pins p   lcdc-rgb565-m1-data-pins p   pwm0pwm0-pin p+\pwm1pwm1-pin p+]pwm2pwm2-pin p +^pwm3pwm3-pin p+_pwm4pwm4-pin p+`pwm5pwm5-pin p+apwm6pwm6-pin p+bpwm7pwm7-pin p+cgmacrmii-pins p +lmac-refclk-12ma p +mmac-refclk p cif-m0cif-clkout-m0 p dvp-d2d9-m0 p   dvp-d0d1-m0 p d10-d11-m0 pcif-m1cif-clkout-m1 pdvp-d2d9-m1 p  dvp-d0d1-m1 pd10-d11-m1 pispisp-prelight pledsmodule-led-pin p+sd-card-led-pin p +pmicpmic-int p+Ihaikouhaikou-keys-pinP p+uartuart5-rts-pin p +Femmc-pwrseqmmc-pwrseq-emmcrddefault ~ +xleds gpio-ledsddefaultrokayled-0  heartbeat heartbeat led-1 [  mmc2 sd vccsys-regulatorregulator-fixed vcc5v0_sysr-LK@ELK@+Jchosen serial0:115200n8gpio-keys gpio-keysrddefaultbutton-batlow-n BATLOW#  [button-slp-btn-n SLP_BTN#  button-wake-n WAKE#  switch-lid-btn-n LID_BTN#   [i2s0-soundsimple-audio-card i2s Haikou,I2S-codec  ' Fsimple-audio-card,codec h r+simple-audio-card,cpu hsgtl5000-oscillator fixed-clock%w+Mdc-12v-regulatorregulator-fixeddc_12vr-E+vcc3v3-baseboard-regulatorregulator-fixedvcc3v3_baseboardr-2ZE2Z +Ovcc5v0-baseboard-regulatorregulator-fixedvcc5v0_baseboardr-LK@ELK@ +vdda-codec-regulatorregulator-fixed vdda_codec-2ZE2Z +Nvddd-codec-regulatorregulator-fixed vddd_codec-jEj +P compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0mmc1rtc0rtc1ethernet0mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cellsrockchip,trcm-sync-tx-only#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio-oscgpi-supplyphysphy-namesrockchip,outputremote-endpointrts-gpiosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendVDDA-supplyVDDIO-supplyVDDD-supplypagesizevcc-supplynum-cscs-gpios#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usphy-supplyclock_in_outbus-widthfifo-depthmax-frequencyvqmmc-supplysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50cap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplymmc-hs200-1_8vmmc-pwrseqnon-removableiommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsoutput-highline-namegpio-hoginputbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-lowinput-enablerockchip,pinsreset-gpiosfunctionlinux,default-triggercolorstdout-pathlabellinux,codelinux,input-typesimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssimple-audio-card,frame-mastersimple-audio-card,bitclock-mastersound-daisystem-clock-fixedvin-supply